The present invention relates to an asymmetry correcting circuit adapted for correction of a vertically asymmetric distortion (asymmetry) of a read waveform generated in a read mode in a digital recording/reproducing apparatus, such as an optical disk apparatus or the like, and also to a recording/reproducing apparatus using such an asymmetry correcting circuit.
In the conventional hard disk devices (HDD) and the like known heretofore, a variety of methods have been contrived for correcting a nonlinear distortion of a read amplifier connected to a magnetoresistance (MR) type head, and such methods are classified broadly into the following three.
The first is a method of canceling the distortion of a read signal by detecting an asymmetry quantity from analog or sampling data, and then feeding back the detected quantity to a bias current of the MR element.
The second is a method of correcting the distortion by subtracting the secondary component of the analog signal. The quantity to be corrected is adjusted by detecting the distortion quantity and forming a negative feedback loop.
The third is a method carried out by detecting the distortion of sampling data and canceling the distortion through digital operation. In this case, there are required a correction quantity detection circuit and a negative feedback loop.
Generation of such asymmetry in an optical disk apparatus is derived from the phenomenon that the length and the width of optical pits recorded on the surface of an optical disk are deviated from reference values by, for example, some variation in the optical power of a laser beam splitter in a recording mode.
In another case where signals are recorded on a single optical disk by a plurality of different recording apparatus, the dimensions of pits recorded on the optical disk are changed, with regard to the same data, due to variations in the performance of the individual recording apparatus, so that when the disk is played continuously, the amplitudes of the reproduced signals are varied to consequently generate some asymmetry in the reproduced signals.
Thus, in the case of an optical disk, nonlinear distortion is generated by variation in a writing power and the medium is replaceable, so that the distortion quantity is changed in each sector (segment), even on the same disk, whereby it is rendered necessary to absorb such variation in a short time within the period of a VFO (training pattern).
For correction of such asymmetry in an optical disk apparatus, adopting any of the first to third methods mentioned above is considered undesirable due to the following reasons.
The first method is restricted merely to an MR read amplifier, and it is not usable in case the factors of generating a distortion are different as in an optical disk.
In the second method, a circuit for correction of the signal is required, and there exists a possibility that some distortion and noise are additionally generated by such a correcting circuit.
Regarding a method for correction of a secondary distortion, an example of subtracting the square component of the signal from its original signal is disclosed in Japanese Patent Laid-open No. Hei 9-134501.
In this method, however, there is known a disadvantage that a tertiary distortion is worsened. Since the DC (direct current) offset of the output signal is varied by the action of the circuit, there arises another problem, when a fast action is needed, with respect to the offset absorption time in an AC (alternating current) coupler provided in the following stage.
In the third method that feeds back the correction quantity through a digital operation after quantization, the gain is limited due to generation of a long loop delay, whereby it is rendered impossible to establish the correction quantity in a short time.
As for the correction method including a digital operation, it is a premise that a PLL (phase-locked loop) is locked to the input signal. Therefore, in case the input signal has a great asymmetry or offset, there exists a possibility that the PLL fails to be locked and consequently the loop breaks down.
Another method is proposed, for example, in Japanese Patent Laid-open No. Hei 8-83403, wherein the median VRC of the quantization reference voltage of an analog-to-digital converter (hereinafter referred to as ADC) is changed, in conformity with the asymmetry of the input signal, to the upper limit VRT and the lower limit VRB of the quantization reference voltage, hence changing the quantization resolutions on the upper and lower sides to eventually cancel the vertical asymmetry of the input signal.
However, the DVR (Digital Video Recorder) system has data of two values on each of the upper and lower sides (four values of xc2x11 and xc2x12 in total), wherein the xc2x11 levels are not changed substantially by the asymmetry while the xc2x12 levels are affected much.
Consequently, it is impossible by the above method to realize effective elimination of the asymmetry by changing only the median VRC of the quantization reference voltage.
Further, since the maximum amplitude of the signal is increased by the asymmetry, there may occur a phenomenon that the amplitude is raised out of the dynamic range of the ADC.
The present invention has been accomplished in view of the circumstances described above. And an object of the invention is to provide an improved asymmetry correcting circuit and an information reproducing apparatus using such a correcting circuit, wherein, when a read signal is processed in a digital recording/reproducing apparatus, the quantization reference level of an ADC for converting the input signal into a digital signal can be changed asymmetrically in accordance with the vertically asymmetric quantity (asymmetry) of the input waveform, the asymmetry can be canceled out simultaneously with the quantization, and further the dynamic range of the ADC can be utilized effectively.
According to the first aspect of the present invention, there is provided an asymmetry correcting circuit for correcting a vertically asymmetric distortion of an input signal waveform in an analog-to-digital converter which quantizes the input signal waveform in accordance with a quantization reference voltage and converts the quantized waveform into a digital signal of predetermined bits, the asymmetry correcting circuit including:
a first envelope detection circuit for detecting the envelope of a positive peak of the input signal waveform;
a second envelope detection circuit for detecting the envelope of a negative peak of the input signal waveform;
an adding circuit for outputting a sum voltage of the positive peak voltage obtained from the first envelope detection circuit and the negative peak voltage obtained from the second envelope detection circuit;
a multiplying circuit for multiplying the sum voltage, which is outputted from the adding circuit, by a predetermined offset adjustment coefficient; and
a quantization reference voltage control circuit for shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the analog-to-digital converter DC-wise in conformity with the offset derived from the asymmetry of the input signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity.
According to the second aspect of the present invention, there is provided an asymmetry correcting circuit for correcting a vertically asymmetric distortion of an input signal waveform in an analog-to-digital converter which quantizes the input signal waveform in accordance with a quantization reference voltage and converts the quantized waveform into a digital signal of predetermined bits, the asymmetry correcting circuit including:
a first envelope detection circuit for detecting the envelope of a positive peak of the input signal waveform;
a second envelope detection circuit for detecting the envelope of a negative peak of the input signal waveform;
an adding circuit for outputting a sum voltage of the positive peak voltage obtained from the first envelope detection circuit and the negative peak voltage obtained from the second envelope detection circuit;
a smoothing circuit for smoothing the sum voltage obtained from the adding circuit;
a multiplying circuit for multiplying the smoothed sum voltage, which is obtained from the smoothing circuit, by a predetermined offset adjustment coefficient; and
a quantization reference voltage control circuit for shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the analog-to-digital converter DC-wise in conformity with the offset derived from the asymmetry of the input signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity.
According to the third aspect of the present invention, there is provided an information reproducing apparatus for reproducing, as digital data, information recorded optically on an optical recording medium, including:
an optical reading means for optically reading, from the optical recording medium, a signal corresponding to the recorded information;
an analog-to-digital converter for quantizing the read signal waveform, which is obtained from the optical reading means, in accordance with a quantization reference voltage whose at least upper and lower limits are settable to desired values, and converting the quantized waveform into a digital signal of predetermined bits; and
an asymmetry correcting circuit including:
a first envelope detection circuit for detecting the envelope of a positive peak of the read signal waveform;
a second envelope detection circuit for detecting the envelope of a negative peak of the read signal waveform;
an adding circuit for outputting a sum voltage of the positive peak voltage obtained from the first envelope detection circuit and the negative peak voltage obtained from the second envelope detection circuit;
a multiplying circuit for multiplying the sum voltage, which is outputted from the adding circuit, by a predetermined offset adjustment coefficient; and
a quantization reference voltage control circuit for shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the analog-to-digital converter DC-wise in conformity with the offset derived from the asymmetry of the read signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity;
wherein the asymmetry correcting circuit is capable of correcting a vertically asymmetric distortion of the read signal waveform in the analog-to-digital converter.
According to the fourth aspect of the present invention, there is provided an information reproducing apparatus for reproducing, as digital data, information recorded optically on an optical recording medium, including:
an optical reading means for optically reading, from the optical recording medium, a signal corresponding to the recorded information;
an analog-to-digital converter for quantizing the read signal waveform, which is obtained from the optical reading means, in accordance with a quantization reference voltage whose at least upper and lower limits are settable to desired values, and converting the quantized waveform into a digital signal of predetermined bits; and
an asymmetry correcting circuit including:
a first envelope detection circuit for detecting the envelope of a positive peak of the read signal waveform;
a second envelope detection circuit for detecting the envelope of a negative peak of the read signal waveform;
an adding circuit for outputting a sum voltage of the positive peak voltage obtained from the first envelope detection circuit and the negative peak voltage obtained from the second envelope detection circuit;
a smoothing circuit for smoothing the sum voltage obtained from the adding circuit;
a multiplying circuit for multiplying the smoothed sum voltage, which is outputted from the smoothing circuit, by a predetermined offset adjustment coefficient; and
a quantization reference voltage control circuit for shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the analog-to-digital converter DC-wise in conformity with the offset derived from the asymmetry of the read signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity;
wherein the asymmetry correcting circuit is capable of correcting a vertically asymmetric distortion of the read signal waveform in the analog-to-digital converter.
According to the present invention, the read signal outputted from the optical read means is processed by the AC connection means so that the DC component of the signal is removed, and then the read signal is supplied to the asymmetry correcting circuit and the ADC.
The read signal thus supplied to the asymmetry correcting circuit is inputted to the first and second envelope detection circuits.
In the first envelope detection circuit, there is detected the envelope of the positive peak of the read signal waveform where the DC component has been removed, and then the detected envelope is outputted to the adding circuit.
Meanwhile in the second envelope detection circuit, there is detected the envelope of the negative peak of the read signal waveform where the DC component has been removed, and then the detected envelope is outputted to the adding circuit.
Subsequently in the adding circuit, a sum voltage is produced by adding the positive peak voltage obtained from the first envelope detection circuit and the negative peak voltage obtained from the second envelope detection circuit, and the sum voltage is outputted to the smoothing circuit.
Thereafter, in the smoothing circuit, the sum voltage obtained from the adding circuit is smoothed and then is outputted to the multiplying circuit.
Here, to cancel the asymmetric distortion of the signal and also to render the PLL circuit lockable for example, a process is executed for attaining a coincidence between the original zero crossing point of the input signal (read signal) and the zero reference voltage VRC of the ADC.
More specifically, the output signal of the smoothing circuit is multiplied by a desired coefficient in the multiplying circuit, and the result is supplied to the quantization reference voltage control circuit.
Then, in the quantization reference voltage control circuit supplied with the signal multiplied by the coefficient, the output signal of the multiplying circuit is subtracted from the bias voltage of the ADC, whereby the zero reference voltage VRC of the ADC is adjusted.
Feedback is applied in such a manner that, for example, the zero reference voltage VRC coincides with the bias voltage V of the ADC, and the offset is adjusted by the first adjusting circuit.
Meanwhile, in the second adjusting circuit, the output signal of the multiplying circuit is multiplied by a coefficient ASYMGT conforming with the correlation between the offset quantity of the read signal (input signal) and the asymmetric distortion quantity thereof, whereby a first adjustment quantity is produced, then the upper limit VRT of the quantization reference voltage is adjusted on the basis of the first adjustment quantity, and the adjusted upper limit VRT is supplied to the ADC.
In the third adjusting circuit, the output signal of the multiplying circuit is multiplied by a coefficient ASYMGB conforming with the correlation between the offset quantity of the read signal (input signal) and the asymmetric distortion quantity thereof, whereby a second adjustment quantity is produced, then the lower limit VRB of the quantization reference voltage is adjusted on the basis of the second adjustment quantity, and the adjusted lower limit VRB is supplied to the ADC.
In the ADC where the bias voltage is applied, the input signal is quantized in accordance with the quantization reference voltage supplied from the quantization reference voltage generating circuit in the asymmetry correcting circuit, then the signal is converted into digital data of predetermined bits, and the digital data is outputted to the data processing circuit.
In the data processing circuit, a predetermined process of equalization is executed by, e.g., an equalizer with regard to the digital data obtained from the ADC, and then the data after such equalization is decoded by a Viterbi decoder.
Also in the data processing circuit, after the PLL circuit is phase-locked, for example, the offset error and the asymmetry error relative to a desired expected value are detected on the basis of the digital data, and correction signals for canceling out such errors are fed back, so that the offset and the asymmetry of the input signal are corrected with high precision.
Thus, the ADC is employed to digitize the input signal when processing the read signal in the reproducing apparatus, wherein the quantization reference level of the ADC is changed asymmetrically in accordance with the vertically asymmetric distortion (hereinafter referred to as asymmetry) of the input waveform. Consequently, the asymmetry can be canceled simultaneously with the quantization, and the dynamic range of the ADC can be utilized effectively.
In other words, the asymmetry correcting circuit of the present invention is characterized by extraction of the correction quantity from the input analog signal of the ADC through processing the analog signal, and also by feed-forward of the extracted control quantity to the quantization reference value of the ADC, hence realizing a fast action of the correcting circuit and exact correction of the asymmetry without the necessity of locking the PLL.
Moreover, the upper limit VRT and the lower limit VRB of the quantization reference voltage of the ADC are controlled independently of each other with respect to xc2x11 data reference values after sampling (e.g., xc2x18 LSB of a 6-bit ADC in a DVR system), thereby attaining effective elimination of the asymmetry in the DVR system.
The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference symbols.